This invention relates generally to electronic integrated circuits (ICs) and more particularly the invention relates to passive devices such as inductors and capacitors of an IC having reduced parasitic substrate capacitance.
The quality, Q, of inductors and capacitors is a strong function of the losses within such devices. Losses can be caused by parasitic series resistances or parasitic shunting capacitances for example. High quality IC inductors and capacitors are required in order to realize on-chip matching elements, narrow-band circuits, filter networks, and transformers, for example. However, typical integrated inductors and capacitors on silicon substrates have low quality factor due to the parasitic capacitance with the substrate. The typical Q for a silicon substrate is in the range of 3 to 6 . In high power RF applications, higher quality elements are required in order to minimize power losses since the parasitic capacitance will shunt to the substrate some of the RF signal.
IC inductors consist of metal spirals formed on thick oxides and high-resistivity epitaxial silicon substrates. The high dielectric constant of the layers under the spiral inductor result in significant parasitic capacitance. See FIGS. 1A and 1B which are a section view of a metal spiral inductor 10 formed on a thick field oxide 12 on a high resistivity epitaxial silicon layer 14 and grounded substrate 16. As shown in the schematic of FIG. 1B, the inductor 10 has parasitic capacitance 18 with the epitaxial layer 14 and substrate 16. Prior art structures for increasing the quality of inductive devices in an IC include etching the silicon substrate under the capacitive structures and thereby forming a low dielectric constant air gap between the capacitive devices and the substrate. See for example Chang et al."Large Suspended Inductors on Silicon and Their Use in a 2.mu.m CMOS RF Amplifier" IEEE Electron Device Letters, vol. 14 , No. 5, May 1993; Ribas et al."Micromachined Planar Spiral Inductor in Standard GaAs HEMT MMIC Technology" IEEE Electron Device Letters, vol. 19 , No. 8 , August 1998; Paek et al. "Air-Gap Stacked spiral Inductor" IEEE Microwave and Guided Wave Letter, Vol. 7, No. 10, Oct. 1997. Other techniques used to form high quality inductors with low parasitic capacitance include the use of a thick polyimide material under the inductors. However, this requires complex processing with a back-end process which is not compatible with temperatures greater than 450.degree. C. Additionally, very thick oxides have been used to separate the metal layers from the underlying substrate. However, when film thickness increases, stress increases resulting in cracking and peeling. Further, long deposition times are required. U.S. Pat. No. 5,742,091 to Hebert teaches the formation of deep trenches under inductors to minimize parasitic capacitance.
The present invention is directed to a process and resulting structure for a passive device having high quality and which is compatible with high temperature standard silicon processing which can be implemented at the beginning, middle, or end of an integrated circuit fabrication process.